1. Field of the Invention
The present invention concerns digital transmission and in particular time-division multiplex digital transmission.
2. Description of the Prior Art
The frame structures of time-division multiplex digital bit streams vary according to the bit rate of the tributaries to be multiplexed and are mostly the subject of CCITT recommendations.
They usually include time slots reserved for transmitting information signals representing the traffic payload and time slots reserved for transmitting auxiliary signals such as order wire or justification signals.
The present invention is more particularly concerned with a device for inserting bits constituting a digital bit stream having a given bit rate into time slots of a given frame structure reserved for transmitting information signals.
The invention is particularly applicable to the construction of frames for time-division multiplexed digital bit streams produced by multiplexing digital tributaries at different bit rates using a synchronous multiplexing hierarchy as defined in CCITT Recommendations G.707, G.708 and G.709.
The theory of a multiplexing hierarchy of this kind is outlined in FIG. 1. The various bit rates that can be multiplexed by this hierarchy are the bit rates of 2 408 kbit/s, 8 448 kbit/s, 34 368 kbit/s, 1 554 kbit/s, 6 312 kbit/s, 44 736 kbit/s and 139 264 kbit/s recommended by the CCITT and listed down the righthand side of this figure.
There are various possible multiplexing structures for this multiplexing hierarchy depending on the bit rates of the tributaries to be multiplexed for a given application, and each multiplexing structure (such as that shown in bold line in this figure) representing tributaries to be multiplexed with bit rates of 1 544 kbit/s, 2 048 kbit/s, 8 448 kbit/s and 34 368 kbit/s comprises a number of hierarchy levels, denoted N1, N2, N3 in the example under consideration, running from right to left in the figure, in the direction in which the frames are constructed from the various tributaries.
Tributaries can be introduced and entities called containers and entities called multiplexing units can be constituted at the various hierarchy levels of a multiplexing structure. The multiplexing units constituted at a given hierarchy level and denoted TU or AU (TU11, TU12, TU22 for level N1, TU31 for level N2 and AU4 for level N3 in the example under consideration) are formed by adding to the containers constituted at the same hierarchy level signals for indexing and justifying these containers relative to these multiplexing units.
The containers constituted at a given hierarchy level and denoted VC (VC11, VC12, VC22 for level N1, VC31 for level N2 and VC4 for level N3 in the example under consideration) are each formed by adding auxiliary signals, either to a multiplex signal obtained by multiplexing together multiplexing units constituted at a lower hierarchy level, or to an information signal sampled on a tributary introduced at the level in question and denoted C (C11, C12, C22 for level N1 and C31 for level N2 in the example under consideration).
In the context of its application to the constitution of such frames, the invention is more specifically used to insert tributaries into containers. The following description makes particular reference to the insertion of a 139 264 kbit/s tributary C4 into a container VC4.
FIG. 2 shows the frame structure of a container VC4 as defined by the previously mentioned CCITT recommendations, the container VC4 being divided into superframes each formed by a succession of nine such frames.
As shown in this figure, the bits of the 139 264 kbit/s digital bit stream C4 are inserted into this frame in groups of twelve (unreferenced) bytes called information bytes and are separated by bytes X and Y called systematic insertion bytes. The first group of twelve bytes is preceded by a byte W assigned to the transmission of information bits, the byte W being itself preceded by a systematic insertion byte. The last group of twelve bytes is similarly preceded by a specific byte Z assigned partly to transmitting information bits I. The eighth bit of byte Z is a stuff bit R which is ignored when the frames of the container VC4 are received. The seventh bit of the byte Z is a justification opportunity bit S for the tributary C4 relative to the container VC4 for the frame in question and can therefore be either an information bit or a stuff bit, depending on the justification state of this frame.
Justification is a standard technique for matching the rate of the bits to be inserted and the bit insertion rate. In the example under consideration, where the justification is positive justification, the S bit of a frame is an information bit of the tributary C4 unless this tributary is justified relative to the container VC4 for the frame in question, in which case the S bit is a stuff bit. The justified or non-justified state of a frame is indicated by the value of a justification control bit C, the C bit occupying in this instance the first location of the systematic insertion bytes X.
The use of this technique conventionally requires a buffer memory into which the incoming information bits are written under the control of a write clock at the clock rate of these bits and which is read under the control of a read clock at the insertion clock rate and a comparator for comparing the phase of the write and read clocks and commanding justification as needed according to the comparison result. When justification is applied, the insertion of a justification opportunity bit in place of an information bit imposes a delay in the insertion of this information bit which is obtained by a corresponding adjustment of the buffer memory read timing.
In the example under consideration the bit rates are 139 264 kbit/s and 155 520 kbit/s. With some technologies the device performing the insertion cannot operate directly at these bit rates but only at reduced bit rates requiring division of the incoming and outgoing digital bit streams into N reduced bit rate digital bit streams, in which case the buffer memory principle mentioned above is no longer directly applicable.
An objective of the present invention is to provide an insertion device enabling operation at reduced bit rates.